PACKAGES USE SEMICONDUCTOR

Brand	Owner (click to sort)	Address	Description
HYPERPAC	SHINKO DENKI KOGYO KABUSHIKI KAISHA	80, Oshimada-machi, Nagano-shi Nagano 381-2287 Japan	packages for use in semiconductor devices and parts therefor, namely, integrated circuit assemblies having a semiconductor element(s) which is connected to a conductive circuit(s) and sealed; integrated circuits, automated bonding tapes, leadframes, glass-to-metal seals, hermetic seal headers and ceramic packages for integrated circuit assemblies and optoelectronic assemblies;HYPER PACK;
HYPERQUAD	SHINKO DENKI KOGYO KABUSHIKI KAISHA	80, Oshimada-machi, Nagano-shi Nagano 381-2287 Japan	packages for use in semiconductor devices and parts therefor, namely integrated circuit assemblies having a semiconductor element(s) which is connected to a conductive circuit(s) and sealed; integrated circuits, automated bonding tapes, leadframes, glass-to-metal seals, hermetic seal headers and ceramic packages for integrated circuit assemblies and optoelectronics assemblies;HYPER - QUAD;
MAAP	SHINKO DENKI KOGYO KABUSHIKI KAISHA	80, Oshimada-machi, Nagano-shi Nagano 381-2287 Japan	packages for use in semiconductor devices and parts therefor, namely integrated circuit assemblies having a semiconductor element(s) which is connected to a conductive circuit(s) and sealed; integrated circuits, automated bonding tapes, leadframes, glass-to-metal seals, hermetic seal headers and ceramic packages for integrated circuit assemblies and optoelectronics assemblies;
THINQUAD	SHINKO DENKI KOGYO KABUSHIKI KAISHA	80, Oshimada-machi, Nagano-shi Nagano 381-2287 Japan	packages for use in semiconductor devices and parts therefor, namely integrated circuit assemblies having a semiconductor element(s) which is connected to a conductive circuit(s) and sealed; integrated circuits, automated bonding tapes, leadframes, glass-to-metal seals, hermetic seal headers and ceramic packages for integrated circuit assemblies and optoelectronics assemblies;THIN QUAD;
	Where the owner name is not linked, that owner no longer owns the brand

Technical Examples

Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.