SEMICONDUCTOR WAFER FABRICATION SERVICES

Brand Owner Address Description
EMPOWERING INNOVATION TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED No. 8, Li-Hsin Road 6 Hsin-Chu Science Park Hsin-Chu Taiwan Semiconductor wafer fabrication services; packing and assembly services for integrated circuits; integrated circuit mask making services, and assembly services for electronic chips and computer chips; all of the aforementioned are made to the order and specification of others;semiconductor integrated circuit; wafer of integrated circuit; photo masks in the nature of transparent quartz plates covered with chrome patterns used in photolithography for making integrated circuits; software for design of integrated circuits; semiconductor chips;providing services regarding semiconductor integrated circuit design, development and technology consultation via international communication network; providing information regarding semiconductor integrated circuit design and development to customer's order; providing consulting services for integrated circuit design; mask design services; providing lease, supply, design, development, modification, establishing, analysis, consultation, access, time-measuring, management, design and compiling, as well as coordinating and planning for the database of semiconductor process equipment, integrated circuit design device and process technology; technology development and system analysis of program designing and development for the database of semiconductor chip process equipment, integrated circuit design device and process technology; providing design service for semiconductor wafer via the global internet connection; providing software data for designing the integrated circuit process technology, device and circuitry via the global internet connection; testing service for mask and integrated circuit on electronic chip;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.