SEMICONDUCTOR MICROELECTRONICS NATURE

Brand Owner Address Description
ALTIS ALTIS SEMICONDUCTOR 91 rue du Faubourg Saint Honoré F-75008 PARIS France Semiconductor microelectronics in the nature of microprocessors, logic circuits, semiconductor memories and logic microcontroller; mobile personal multimedia devices in the nature of semiconductor devices, namely, logic circuits and electronic memories; integrated circuits being off the-shelf components for connecting portable computer devices to computer or telecommunication networks; integrated circuits being off the-shelf components; integrated circuits; integrated circuit chips; semiconductor processors, semiconductor processing chips; microprocessors; printed circuit boards, electronic circuit boards, semiconductor memory; semiconductor devices; instruction guides, specifications and design rules featuring descriptions in the field of semiconductor design, test adaptors for testing semiconductor devices on circuit boards;AITIS LOGIC TECHNOLOGY IN SILICON;Color is not claimed as a feature of the mark.;The wording ALTIS has no meaning in a foreign language.;Development and design of new technology for others in the field of microchips; design of integrated circuits in the field of integrated semiconductor components that allow for rapid development of new semiconductor products, integrated circuits being off- the-shelf components system design services, technical consulting in the fields of central processor units and semiconductors, namely, development, production, packaging, checking the compatibility of one semiconductor product, namely, application specific integrated circuits or application specific standard product, namely, integrated circuits being off the-shelf components with another, development being design of microprocessors; development being design of semiconductors;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.