REDUCED INSTRUCTION SET COMPUTER BASED

Brand	Owner	Address	Description
MILLENNIUM 4000	MIPS COMPUTER SYSTEMS, INC.	930 ARQUES AVENUE SUNNYVALE CA 940863650	reduced instruction set computer based computers and computer components;
	Where the owner name is not linked, that owner no longer owns the brand

Technical Examples

A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.