EXTENSIONS INSTRUCTION SET ARCHITECTURES

Brand Owner Address Description
MICROMIPS MIPS TECH 780 Montague Expressway Ste 308 San Jose CA 95131 Extensions to instruction set architectures for the development and design of semiconductor devices; [ computer operating system software; ] programming models in the nature of computer hardware and software development tools for microprocessor-based semiconductor devices used in transmitting data to and from central processing units; publications recorded on computer media and downloadable electronic publications in the nature of manuals, instructions guides, specification and data sheets, all for use in connection with the design and development of microprocessor based semiconductor devices;MICRO MIPS;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.