DESIGN TESTING INTEGRATED

Brand Owner (click to sort) Address Description
NEOMTP eMemory Technology Inc. ROOM 305, NO. 47, PARK AVENUE II RD. SCIENCE-BASED INDUSTRIAL PARK HSINCHU 30076 R.O.C. Taiwan Design and testing of integrated circuits for others; testing and analysis of integrated circuits of others for the purpose of certification; design and testing of semiconductor chips and integrated circuits for others; semiconductor integrated circuit design and consultation in the field of design of semiconductor integrated circuits; integrated circuit design consultation; technical consultation in the field of integrated circuit design;
NEOROM eMemory Technology Inc. ROOM 305, NO. 47, PARK AVENUE II RD. SCIENCE-BASED INDUSTRIAL PARK HSINCHU 30076 R.O.C. Taiwan Design and testing of integrated circuits for others; testing and analysis of integrated circuits of others for the purpose of certification; design and testing of semiconductor chips and integrated circuits for others; semiconductor integrated circuit design and consultation; integrated circuit design consultation; technical consultation in the fields of integrated circuit design, and data transformation and fabricating procedures with respect to integrated circuits;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.