ALVAREZ MARSAL CONTEXT

Brand Owner (click to sort) Address Description
A&M CONTEXT Alvarez & Marsal Holdings 600 Madison Ave. New York NY 10022 ALVAREZ AND MARSAL CONTEXT;Software as a service (SAAS) services featuring software, namely, a customizable software platform which collects, analyzes, connects, extends and refines unstructured and structured data to understand it quickly and identify patterns, trends and anomalies; consulting services offered in conjunction with a data-as-a-service, namely, a customizable software platform which collects, analyzes, connects, extends and refines unstructured and structured data to understand it quickly and identify patterns, trends and anomalies;
ALVAREZ & MARSAL CONTEXT Alvarez & Marsal Holdings 600 Madison Ave. New York NY 10022 ALVAREZ AND MARSAL CONTEXT;Software as a service (SAAS) services featuring software, namely, a customizable software platform which collects, analyzes, connects, extends and refines unstructured and structured data to understand it quickly and identify patterns, trends and anomalies; consulting services offered in conjunction with a data-as-a-service, namely, a customizable software platform which collects, analyzes, connects, extends and refines unstructured and structured data to understand it quickly and identify patterns, trends and anomalies;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the SP/PE-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array SP/PE-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file. In arrays consisting of more than a single PE, the software controllable context switch mechanism is used to reconfigure the array to take advantage of the multiple context support the merged SP/PE provides. For example, a 1×1 can be configured as a 1×1 with context-0 and as a 1×0 with context-1, a 1×2 can be configured as a 1×2 with context-0 and as a 1×1 with context-1, and a 1×5 can be configured as a 1×5 with context-0 and as a 2×2 with context-1. Other array configurations are clearly possible using the present techniques. In the 1×5/2×2 case, the two contexts could be a 1×5 array (context-0) and a 2×2 array (context-1).